1. Field of the Invention
The present invention relates to an information device such as a computer or peripheral devices of a computer, and in particular to data transfer operations between CPU, RAM, and I/O channels.
2. Description of the Prior Art
An information device such as a computer or peripheral devices of a computer usually comprises a CPU, a RAM, and an I/O channel. The information device typically handles data in the following manner: data is retrieved via the I/O channel from an external memory device such as a magnetic disk device and then transferred to the RAM; the data stored on the RAM are then processed by means of the CPU; and the processed data are then transferred back to the external memory device via the I/O channel. Occasionally a plurality of RAMs and I/O channels are employed in the information device. In some cases, data transfer is required between one I/O channel and another I/O channel or between one RAM and another RAM.
To transfer data between one RAM and one I/O channel, between one I/O channel and another I/O channel, or between one RAM and another RAM in the information the CPU performs a two-step operation: (1) reading data from the I/O channel in the first step, and then (2) writing the read data onto the RAM. Alternatively, a dedicated DMA controller for data transfer is employed; the control of data bus may be taken over by the DMA controller from the CPU, and the data transfer is thus performed by the DMA controller.
In the conventional information device, data transfer, for example, from the RAM to the I/O channel takes two steps: the CPU reads data from the RAM and writes the read data onto the I/O channel. Similarly, data transfer in the opposite direction, i.e., from the I/O channel to the RAM, takes two steps. Therefore, there has been a problem that, when fast data transfer is required, data transfer rate is not high enough. When a dedicated DMA controller is employed, a sufficiently high transfer rate is not achieved because of overhead involved in the takeover operation of the data bus control to the DMA controller from the CPU.
Similarly, there has been a problem that, when in a data transfer operation between one I/O channel and another I/O channel or between one RAM and another RAM, sufficiently high data transfer rate cannot be achieved.